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femtoclocks? crystal-to- lvcmos/lvttl clock generator ics840001 idt ? / ics ? lvcmos/lvttl clock generator 1 ics840001bg rev. a june 13, 2007 g eneral d escription the ics840001 is a fibre channel clock generator and a member of the hiperclocks tm family of high performance devices from idt. the ics840001 uses a 26.5625mhz crystal to synthesize either 106.25mhz or 212.5mhz, using the freq_sel pin. the ics840001 has excellent phase jitter performance, over the 637khz ? 10mhz integration range. the ics840001 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? one lvcmos/lvttl output, 7 typical output impedence ? crystal oscillator interface designed for 26.5625mhz, 18pf parallel resonant crystal ? selectable 106.25mhz or 212.5mhz output frequency ? vco range: 560mhz to 680mhz ? rms phase jitter @ 106.25mhz, using a 26.5625mhz crystal (637khz - 10mhz): 0.696ps (typical) ? rms phase noise at 106.25mhz (typical) phase noise: offset noise p o w er 100hz ............... -94.4 dbc/hz 1khz ............. -119.9 dbc/hz 10khz ......... .... -130.2 dbc/hz 100khz ......... .... -131.5 dbc/hz ? 3.3v operating supply ? -30c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s ics840001 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view v dda oe xtal_out xtal_in 1 2 3 4 v dd q0 gnd freq_sel 8 7 6 5 t u p n i s e i c n e u q e r f t u p t u o l e s _ q e r f 0) t l u a f e d ( z h m 5 2 . 6 0 1 1z h m 5 . 2 1 2 z h m 5 2 6 5 . 6 2 : l a t s y r c b lock d iagram p in a ssignment f unction t able osc phase detector vco 637.5mhz w/ 26.5625mhz ref. m = 24 (fixed) 1 0 6 3 xtal_in xtal_out oe q0 freq_sel (pullup) (pulldown)
idt ? / ics ? lvcmos/lvttl clock generator 2 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator t able 2. p in c haracteristics t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v a d d r e w o p. n i p y l p p u s g o l a n a 2e ot u p n ip u l l u p . d e l b a n e s i t u p t u o 0 q , h g i h n e h w . n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e t a t s z - i h o t 0 q s e c r o f , w o l n e h w 4 , 3 , t u o _ l a t x n i _ l a t x t u p n i . t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 5l e s _ q e r ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 6d n gr e w o p. d n u o r g y l p p u s r e w o p 70 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c d e d n e - e l g n i s 7 . e c n a d e p m i t u p t u o l a c i p y t 8v d d r e w o p. n i p y l p p u s e r o c : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o pv d d v , a d d v 5 6 4 . 3 =4 2f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o572 1 t able 3. c ontrol f unction t able s t u p n i l o r t n o ct u p t u o e o0 q 0z - i h 1e v i t c a
idt ? / ics ? lvcmos/lvttl clock generator 3 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 101.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v dd = v dda = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 8a m i a d d t n e r r u c y l p p u s g o l a n a 0 1a m t able 5. c rystal c haracteristics t able 4b. lvcmos/lvttl dc c haracteristics , v dd = v dda = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i l e s _ q e r fv d d v = n i v 5 6 4 . 3 =0 5 1a e ov d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i l e s _ q e r fv d d v , v 5 6 4 . 3 = n i v 0 =5 -a e ov d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t d d , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2 6 5 . 6 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p
idt ? / ics ? lvcmos/lvttl clock generator 4 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator t able 6. ac c haracteristics , v dd = v dda = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 1 = l e s _ q e r f6 6 . 6 8 15 . 2 1 26 6 . 6 2 2z h m 0 = l e s _ q e r f3 3 . 3 95 2 . 6 0 13 3 . 3 1 1z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n , z h m 5 2 . 6 0 1 = t u o f ) z h m 0 1 o t z h k 7 3 6 ( 6 9 6 . 0s p , z h m 5 . 2 1 2 = t u o f ) z h m 0 2 o t z h m 5 5 . 2 ( 8 5 4 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 6s p c d oe l c y c y t u d t u p t u o z h m 5 2 . 6 0 1 = t u o f8 42 5% z h m 5 . 2 1 2 = t u o f5 45 5% . z h m 5 2 . 6 0 1 d n a z h m 5 . 2 1 2 @ d e z i r e t c a r a h c e r a s r e t e m a r a p l l a . s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n
idt ? / ics ? lvcmos/lvttl clock generator 5 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator t ypical p hase n oise at 106.25mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m 106.25mhz rms phase jitter (random) 637k to 10mhz = 0.696ps (typical) o ffset f requency (h z ) n oise p ower dbc hz phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ? 212.5mhz rms phase jitter (random) 2.55mhz to 20mhz = 0.458ps o ffset f requency (h z ) n oise p ower dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ? t ypical p hase n oise at 212.5mh z
idt ? / ics ? lvcmos/lvttl clock generator 6 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator scope qx lvcmos gnd p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit 1.65v 5% -1.65v 5% clock outputs 20% 80% 80% 20% t r t f t period t pw t period odc = v ddo 2 x 100% t pw q0 v dd, v dda rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
idt ? / ics ? lvcmos/lvttl clock generator 7 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator a pplication i nformation i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput p ins as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics840001 provides separate power supplies to isolate any high switching noise from the out- puts to the internal pll. v dd , and v dda should be individually con- nected to the power supply plane through vias, and bypass ca- pacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illus- trates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd
idt ? / ics ? lvcmos/lvttl clock generator 8 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator f igure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics840001 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 26.5625mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted fordifferent board layouts. c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xtal _i n xtal _ou t .1uf rs
idt ? / ics ? lvcmos/lvttl clock generator 9 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator l ayout g uideline figure 4a shows a schematic example of the ics840001. an example of lvcmos termination is shown in this schematic. additional lvcmos termination approaches are shown in the lvcmos termination application note. in this example, an 18 pf parallel resonant 26.5625mhz crystal is used. the c1= 27pf and c2 = 33pf are recommended for frequency accuracy. for different f igure 4a. ics840001 s chematic e xample board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. the output frequency can be set at either 106.25mhz or 212.5mhz. leaving the r1 un-installed (or install 1k pull-down) will set the output frequency at 106.25mhz. installing the r1 pull up will set the output frequency at 212.5mhz. pc b oard l ayout e xample figure 4b shows an example of p.c. board layout. the crystal x1 footprint in this example allows either surface mount (hc49s) or through hole (hc49) package. c3 is 0805. c1 and c2 are 0402. other resistors and capacitors are 0603. this layout assumes that the board has clean analog power and ground planes. f igure 4b. ics840001 pc b oard l ayo u t e xample r2 10 c3 10uf lvcmos c4 0.1u vdda q r1 1k zo = 50 ohm c1 27pf r3 43 c2 33pf vdd x1 oe vdd vdd u1 ics840001 1 2 3 4 8 7 6 5 vdda oe xtal_out xtal_in vdd q0 gnd freq_sel fre_sel vdd=3.3v c5 0.1u
idt ? / ics ? lvcmos/lvttl clock generator 10 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator r eliability i nformation t ransistor c ount the transistor count for ics840001 is: 1521 t able 7. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
idt ? / ics ? lvcmos/lvttl clock generator 11 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator p ackage o utline - g s uffix for 8 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? lvcmos/lvttl clock generator 12 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 7. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g b 1 0 0 0 4 8 s c ib 1 0 0p o s s t d a e l 8e b u tc 5 8 o t c 0 3 - t g b 1 0 0 0 4 8 s c ib 1 0 0p o s s t d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - f l g b 1 0 0 0 4 8 s c il b 1 0 0p o s s t " e e r f d a e l " d a e l 8e b u tc 5 8 o t c 0 3 - t f l g b 1 0 0 0 4 8 s c il b 1 0 0p o s s t " e e r f d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? lvcmos/lvttl clock generator 13 ics840001bg rev. a june 13, 2007 ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a9 t1 1 . 0 0 1 o t e b u t r e p 4 5 1 m o r f t n u o c d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 5 1 / 0 1 a 7 t 1 7 8 2 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p n i d e s u n u r o f s n o i t a d n e m m o c e r d e d d a . e c a f r e t n i l a t x o t s o m c v l . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 7 0 / 3 1 / 6
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics840001 femtoclocks? crystal-to-lvcmos/lvttl clock generator

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